Data converters are integral part of various system-on-chip (“SoC”) applications that have precision and speed requirements. A shift to high performance data converters is unavoidable in modern semiconductor fabrication technologies. However, process corner variations in data converters can degrade performance and speed of the data converters; especially due to scaling of nodes, the impact has become even more severe.
To achieve desired performance in terms of resolution, speed of operation, system linearity, and noise margins, SoC designers use a variety of calibration methods for the DAC. Although such calibration methods can provide alignment for the DAC, calibration in a production tester for every component of the DAC can add extra unwanted costs and increase time to market for the DAC.
For instance, U.S. Pat. No. 9,136,864 discloses a DAC that uses current cells that are connected to current trimming modules. The DAC has a plurality of segments and current drivers which are operated at different trim coefficients driven by an external or internal source to adjust the threshold voltage for each segment. To achieve different well biasing, each of the segments need to be placed in different isolated deep N-well. Isolation of the deep N-well islands require more area overhead for the DAC. Though this technique helps to tune a threshold voltage of individual segments, it suffers from mismatches among the segments. Local mismatches are difficult to tune due to limitations for granular control of the back-gate bias voltage of different segments.
To reduce error due to individual cell mismatch, DAC designers may implement regular patterns, such as a double or triple centroid layout for the DAC. Also, different switching schemes have been used and adopted to reduce the internal mismatch of the most significant cells of the DAC. For a higher resolution application, a calibration logic can be used where most significant bit (“MSB”) segments each require separate calibration by adding or subtracting the required amount of current for each of the MSB segments to align them. However, such calibration demands extra chip area and power. Even after maintaining proper layout and design precautions, it would be difficult to reduce these errors to a lower extent suitable for high resolution data converters.
Therefore, it is desirable to provide improved new methods, systems, and circuits for a high-speed DAC. Furthermore, it is desirable to provide for trimming and finer adjustment for the high-speed DAC by providing a control knob(s) for back-gate bias control.